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single supply high speed pecl/lvpecl comparators data sheet adcmp551 / adcmp552 / adcmp553 rev. a document feedback information furnished by analog devices is believed to be accurate an d reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by i mplication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features single power supply 500 ps propagation delay input to output 125 ps overdrive dispersion differential pecl/lvpecl compatible outputs differential latch control internal latch pull - up resistors power supply rejection greater than 70 db 700 ps minim um pulse width equivalent input rise time bandwidth > 750 mhz typical output rise/fall of 500 ps programmable hysteresis applications automatic test equipment high speed instrumentation scope and logic analyzer front ends window comparators high speed li ne receivers threshold detection peak detection high speed triggers patient diagnostics disk drive read channel detection hand - held test instruments zero crossing detectors line receivers and signal restoration clock drivers functional block dia gram fi gure 1 . general description the adcmp551/adcmp552/adcmp553 are single supply, high speed comparato rs fabricated on analog devices proprietary xfcb process. the devices feature a 500 ps propagation delay with less than 125 ps over drive dispersion. overdrive dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. a separate programmable hysteresis pin is available on the adcmp 552. a differential input stage permits consistent propagation delay with a common - mode range from C 0.2 v to vcci C 2.0 v. outputs are complementary digital signals and are fully compatible with pecl and 3.3v lvpecl logic families. the outputs provide sufficient drive current to directly drive transmission lines terminated in 50 ? to vcco ? 2 v. a latch input is included and permits tracking, track - and - hold, or sample - and - hold modes of operation. the latch input pins contain internal pull - ups that set the latch in tracking mode when left open. the adcmp551/adcmp552/adcmp553 are specified over the C 40c to +85c industrial temperature range. the adcmp551 is available in a 16 - lead qsop package; the adcmp552 is available in a 20 - lead qsop package; and the adcmp 553 is available in an 8 - lead msop package. 04722-001 noninverting input inverting input latch enable input q output latch enable input q output adcmp551/ adcmp552/ adcmp553 *adcmp552 only hys*
adcmp551/adcmp552/adcmp553 data sheet rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal considerations .............................................................. 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 8 timing information ....................................................................... 10 applications information .............................................................. 11 clock timing recovery ............................................................. 11 optimizing high speed performance ..................................... 11 comparator propagation delay dispersion ........................... 11 comparator hysteresis .............................................................. 12 minimum input slew rate requirement ................................ 12 typical application circuits ......................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 15 revision history 6/13rev. 0 to rev. a updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 10/04revision 0: initial version
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 3 of 16 specifications v cci = 3.3 v, v cco = 3.3 v, t a = 25 c, unless otherwise noted. table 1 . electrical characteristics parameter symbol conditions min typ max unit dc input characteristics input voltage range ?0. 2 v cci C 2.0 v input differential voltage range ? 3 + 3 v input offset voltage v os ? in = 0 v, +in = 0 v ? 10.0 2.0 + 10.0 mv input offset voltage channel matching 1.0 mv offset voltage tempco v os /d t 2.0 v/c input bias current i in ? in = ?0. 2 v, +in = + 1.3 v ? 28.0 C 6.0 + 5.0 a input bias current tempco C5.0 na/c input offset current ? 3.0 1.0 + 3.0 a input capacitance c in 1.0 pf input resistance, differential mode 1800 k input resistance, common mode 1000 k active gain a v 60 db common - mode rejection ratio cmrr v cm = ? 0.2 v to + 1.3 v 76 db hysteresis r hys = 0.5 mv latch enable characteristics latch enable voltage range v cci C 1.8 v cci C 0.8 v latch enable differential voltage range 0.4 1.0 v latch enable input high current @ v cci C 0.8 v ? 150 + 150 a latch enable input low current @ v cci C 1.8 v ? 150 + 150 a le voltage, open latch inputs not connected v cci C 0.15 v cci v le voltage, open latch inputs not connect ed v cci / 2 C 0.075 v cci / 2 + 0.075 v latch setup time t s v od = 250 mv 100 ps latch hold time t h v od = 250 mv 100 ps latch to output delay t ploh , t plol v od = 250 mv 450 ps latch minimum pulse width t pl v od = 250 mv 700 ps dc output characterist ics output voltage high level v oh pecl 50 to v dd ? 2.0 v v cco ? 1.15 v cco ? 0.78 v output voltage low level v ol pecl 50 to v dd ? 2.0 v v cco ? 2.00 v cco ? 1.54 v ac output characteristics rise time t r 10% to 90% 510 ps fall time t f 10% to 90% 490 ps ac output characteristics ( adcmp553) rise time t r 10% to 90% 440 ps fall time t f 10% to 90% 410 ps ac performance propagation delay t pd v od = 1 v 500 ps v od = 20 mv 625 ps propagation delay tempco t pd /d t v od = 1 v 0.25 ps/c prop delay skew rising tr ansition to falling transition v od = 1 v 35 ps within device propagation delay skew channel -to - channel v od = 1 v 35 ps overdrive dispersion 20 mv v od 100 mv 75 ps overdrive dispersion 50 mv v od 1.0 v 75 ps slew rate dispersion 0.4 v/ns sr 1.33 v/ns 75 ps
ad cmp551/adcmp552/adcmp553 data sheet rev. a | page 4 of 16 parameter symbol conditions min typ max unit ac performance (continued) pulse width dispersion 700 ps pw 10 ns 25 ps duty cycle dispersion 33 mhz, 1 v/ns, v cm = 0.5 v 10 ps common - mode voltage dispersion 1 v swing, 0.3 v v cm 0.8 v 10 ps equ ivalent input rise time bandwidth 1 bw eq 0 v to 1 v swing, 2 v/ns 750 mhz maximum toggle rate > 50% output swing 800 mhz minimum pulse width pw min t pd < 25 ps 700 ps rms random jitter v od = 250 mv, 1.3 v/ns, 500 mhz, 50% duty cycle 1.1 ps uni t -to - unit propagation delay skew 50 ps power supply (adcmp 551 /adcmp 552) input supply current i vcci @ 3.3 v 8 12 17 ma output supply current i vcco @ 3.3 v without load 3 5 9 ma output supply current @ 3.3 v with load 40 55 70 ma input supply voltage v cci dual 3.135 3.3 5.25 v output supply voltage v cco dual 3.135 3.3 5.25 v positive supply differential v cco ? v cci C0.2 + 2.3 v power dissipation p d dual, without load 40 55 75 mw power dissipation dual, with load 90 110 130 mw dc power supply rejection ratio v cci psrr vcci 75 db dc power supply rejection ratio v cco psrr vcco 85 db power supply (adcmp 553 ) positive supply current i vcc @ 3.3 v without load 9 13 ma positive supply current @ 3.3 v with load 35 42 ma positive supply voltage v cc dual 3.135 3.3 5.25 v power dissipation p d dual, without load 30 42 mw power dissipation dual, wit h load 60 75 mw dc power supply rejection ratio v cc psrr vcc 70 db hysteresis (adcmp 552 only) programmable hysteresis 0 40 mv 1 equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: bw eq = .22/ (tr comp 2 ? tr in 2 ), where tr in is the 20/80 input transition time applied to the comparator and tr comp is the effective transition time as digiti zed by the comparator input.
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 5 of 16 absolute maximum rat ings table 2. parameter rating supply voltages input supply volt age (v cci to gnd) ? 0.5 v to + 6.0 v output supply voltage (v cco to gnd) ? 0.5 v to +6.0 v ground voltage differential ? 0.5 v to + 0.5 v input voltages input common - mode voltage ? 0.5 v to + 3.5 v differential input voltage ? 4.0 v to + 4.0 v input voltage, latch controls ? 0.5 v to + 5.5 v output output current 30 ma temperature operating temperature, ambient ? 40 c to + 85 c operating temperature, junction 125 c storage temperature range ? 65 c to + 150 c stresses above those listed under absolute maxim um ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolu te maximum rating conditions for extended periods may affect device reliability. thermal consideratio ns the adcmp551 16 - lead qsop package has a ja (junction - to - ambient thermal resistance) of 104 c/w in still air. the adcmp552 20 - lead qsop package has a ja (junction - to - ambient thermal resistance) of 80 c/w in still air. the adcmp553 8 - lead msop package has a ja (junction - to - ambient thermal resistance) of 130 c/w in still air. esd caution
ad cmp551/adcmp552/adcmp553 data sheet rev. a | page 6 of 16 pin configuration s and function descrip tions figure 2 . adcmp551 16 - lead qsop pin configuration figure 3 . adcmp552 20 - lead qsop pin configuration figure 4 . adcmp553 8 - lead msop pin configuration table 3 . pin function descriptions pin no. mnemonic function adcmp 551 adcmp 552 adcmp 553 3 , 14 1, 4, 17, 20 v cco logic supply terminal. 1 2 6 qa one of two complementary outputs for channel a. qa is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). see the description of pin lea for more information. 2 3 5 qa one of two complementary outputs for channel a. qa is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). see the description of pin lea for more information. 4 5 2 lea one of two complementary outputs for channel a latch enable. in the compare mode (logic high), the output tracks changes at the input of the comparator. in the latch mode (logic low), the output reflects the input state just prior to the comparators being placed in the latch mode. lea must be driven in conjunction with lea. 5 6 1 lea one of two complementary outputs for channel a latch enable. in the compare mode (logic high), the output tracks changes at the input of the comparator. in the latch mode (logic low), the output reflects the input state just prior to the comparators being pl aced in the latch mode. lea must be driven in conjunction with lea . 6 7 v cci input supply terminal. 7 8 4 ? ina inverting analog input of the differential input stage for channel a. the inverting a input must be driven in conjunction wi th the noninverting a input. 8 9 3 +ina noninverting analog input of the differential input stage for channel a. the noninverting a input must be driven in conjunction with the inverting a input. 10 hysa programmable hysteresis. 11 hysb programmable hysteresis. 9 12 +inb noninverting analog input of the differential input stage for channel b. the noninverting b input must be driven in conjunction with the inverting b input. 10 13 ? inb inverting analog input of the differential input stage for channel b. the inverting b input must be driven in conjunction with the noninverting b input. 11 14 8 agnd analog ground. 04722-002 adcmp551 top view (not to scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ?ina +ina qa qa v cco v cci lea lea ?inb +inb qb qb v cco agnd leb leb 04722-003 adcmp552 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ? ina qa qa v cco v cci lea lea v cco +ina hysa ? inb qb qb v cco agnd leb leb v cco +inb hysb 04722-004 adcmp553 top view (not to scale) 1 2 3 4 8 7 6 5 lea lea +ina ? ina agnd v cc qa qa
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 7 of 16 pin no. mnemonic function adcmp 551 adcmp 552 adcmp 553 12 15 leb one of two complementary inputs for cha nnel b latch enable. in the compare mode (logic low), the output tracks changes at the input of the comparator. in the latch mode (logic high), the output reflects the input state just prior to the comparators being placed in the latch mode. leb must be d riven in conjunction with leb . 13 16 leb one of two complementary inputs for channel b latch enable. in the compare mode (logic low), the output tracks changes at the input of the comparator. in the latch mode (logic high), the output r eflects the input state just prior to the comparators being placed in the latch mode. leb must be driven in conjunction with leb . 15 18 qb one of two complementary outputs for channel b. qb is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). see the description of pin leb for more information. 16 19 qb one of two complementary outputs for channel b. qb is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). see the description of pin leb for more information. 7 v cc posit ive supply terminal.
ad cmp551/adcmp552/adcmp553 data sheet rev. a | page 8 of 16 typical performance characteristics v cci = 3.3 v, v cco = 3.3 v, t a = 25 c, unless otherwise noted. figure 5 . input bias current vs. input voltage figure 6 . input offset voltag e vs. temperature figure 7 . adcmp551/2 rise/fall time vs. temperature figure 8 . input bias current vs. temperature figure 9 . rise and fall of outputs vs. time figur e 10 . adcmp553 rise/fall time vs. temperature ?5 ?10 ?9 ?8 ?7 ?6 ?0.2 0.1 0.4 0.7 1.0 1.3 04722-005 noninverting input voltage (inverting voltage = 0.5v) input bias current (a) 2.00 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 ?40 80 60 40 20 0 ?20 04722-006 temperature (c) offset voltage (mv) 525 515 505 495 485 475 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 04722-007 temperature (c) time (ps) rise fall ? 6.5 ? 7.5 ? 7.4 ? 7.3 ? 7.2 ? 7.1 ? 7.0 ? 6.9 ? 6.8 ? 6.7 ? 6.6 ? 40 80 60 40 20 0 ? 20 04722-008 temperature ( c) +in input bias current ( a) (+in = 0.5v, ? in = 0v) 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 0 0.25 0.50 0.75 1.00 rise fall 1.25 1.50 1.75 04722-012 time (ns) output rise and fall (v) 460 440 450 430 420 410 400 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 04722-010 temperature (c) time (ps) rise fall
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 9 of 16 figure 11 . propagation delay vs. temperature figure 12 . propagation delay vs. overdrive voltage figure 13 . comparator hysteresis vs. r hys figure 14 . propagation delay vs. common - mode voltage figure 15 . propagation delay error vs. pulse width figure 16 . comparator h ysteresis vs. i hys 515 480 485 490 495 500 505 510 ? 40 ? 30 ? 20 ? 10 0 10 20 30 40 50 60 70 80 90 04722-011 temperature ( c) propagation delay (ps) 140 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1.0 04722-012 overdrive voltage (v) propagation delay error (ps) 120 100 80 60 40 20 0 100 10 1 04722-009 r hys (k ? ) programmed hysteresis (mv) 505 504 503 502 501 500 499 498 497 496 495 ? 0.2 0.1 0.4 0.7 1.0 1.3 04722-014 input common mode voltage (v) propagation delay (ps) 25 0 5 10 15 20 ? 5 0.7 9.7 8.7 7.7 6.7 5.7 4.7 3.7 2.7 1.7 04722-015 pulse width (ns) propagation delay error (ps) 140 120 100 80 60 40 20 0 0 300 250 200 150 100 50 04722-025 i hys ( a) programmed hysteresis (mv)
ad cmp551/adcmp552/adcmp553 data sheet rev. a | page 10 of 16 timing information figure 17 . system timing diagram figure 17 shows the compare and latch features of the adcmp55x family. tabl e 4 describes the terms i n the diagram. table 4 . timing descriptions mbol timing description t pdh input to output high delay propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low -to - high transition t pdl input to output low delay propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high -to - low transition t ploh latch enable to outpu t high delay propagation delay measured from the 50% point of the latch enable signal low -to - high transition to the 50% point of an output low -to - high transition t plol latch enable to output low delay propagation delay measured from the 50% point of the l atch enable signal low -to - high transition to the 50% point of an output high -to - low transition t h minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held a t the outputs t pl minimum latch enable pulse width minimum time the latch enable signal must be high to acquire an input signal change t s minimum setup time minimum time before the negative transition of the latch enable signal that an input signal chang e must be present to be acquired and held at the outputs t r output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points v od voltage overdrive difference between the differential input and reference input voltages 50% 50% v ref v os 50% differential input voltage latch enable q output q output latch enable t h t pdl t pdh t ploh t plol t r t f v in v od t s t pl 04722-016
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 11 of 16 application s information the comparators in the adcmp55x series are very high speed devices. consequently, hi gh speed design techniques must be employed to achieve the best performance. the most critical aspect of any adcmp55x design is the use of a low impedance ground plane. a ground plane, as part of a multilayer board, is recommended for proper high speed per formance. using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. the ground plane provides a low inductance ground, eliminating any potential differences at d ifferent ground points throughout the circuit board caused by ground bounce. a proper ground plane also minimizes the effects of stray capacitance on the circuit board. it is also important to provide bypass capacitors for the power supply in a high speed application. a 1 f electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. these capacitors reduce any potential voltage ripples from the power supply. in addition, a 10 nf ceramic capacitor should be placed as close to the power supply pins as possible on the adcmp 55 x to ground. these capacitors act as a charge reservoir for the device during high frequency switching. the latch enable input is active low (latched). if the latching function is not used, the latc h enable input pins may be left open. the internal pull - ups on the latch pins set the latch to transparent mode. if the latch is to be used, valid pecl voltages are required on the inputs for proper operation. the pecl voltages should be referenced to v cci . occasionally, one of the two comparator stages within the adcmp551/adcmp552 is not used. the inputs of the unused comparator should not be allowed to float. the high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. this is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the latch enable and latch enable input s as described previously. the best performance is achieved with the use of proper pecl terminations. the open - emitter outputs of the adcmp55x are designed to be termin ated through 50 ? resistors to v cco ? 2.0 v or any other equivalent pecl termination. if high speed pecl signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. clock timing recover y comparators are often used in digital systems to recover clock timing signals. high speed square waves transmitted over a dist - ance, even tens of centimeters, can become distorted due to stray capacitance and inductance. poor layout or improper termin ation can also cause reflections on the transmission line, further dis - torting the signal waveform. a high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. optimizing high spee d performance as with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the adcmp55x. the performance limits of high speed circuitry can easily be a result of stray capacitance, imprope r ground impedance, or other layout issues. minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the adcmp55x. source resistance in combination with equivalent input capacitance can cause a lagged response at the input, thus delaying the output. the input capacitance of the adcmp55x, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. a combination of 3 k? source res istance and 5 pf input capacitance yields a time constant of 15 ns, which is significantly slower than the 500 ps capability of the adcmp 55 x. source impedances should be significantly less than 100 ? for best performance. sockets should be avoide d due to s tray capacitance and inductance. if proper high speed techniques are used, the adcmp55x should be free from oscillation when the comparator input signal passes through the switching threshold. comparator propagati on delay dispersion the adcmp55x has been s pecifically designed to reduce propagation delay dispersion over an input overdrive range of 20 mv to 1 v. propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switchin g point is exceeded by the input). the overall result is a higher degree of timing accuracy since the adcmp 55 x is far less sensitive to input variations than most comparator designs. propagation delay dispersion is an important specification in critical ti ming applications such as ate, bench instruments, and nuclear instrumentation. overdrive dispersion is defined as the variation in propagatio n delay as the input overdrive conditions are changed ( figure 18 ). for the adcmp55x, overdrive dispersion is typic ally 125 ps as the overdrive is changed from 20 mv to 1 v. this specification applies for both positive and negative overdrive since the adcmp 55 x has equal delays for positive - and negative - going inputs.
ad cmp551/adcmp552/adcmp553 data sheet rev. a | page 12 of 16 figure 18 . propagation delay dispersion comparator hysteresi s the addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. the transfer function for a comparator with hysteresis is shown in figure 19 . if the input voltage approaches the threshold from the negative direction, the comparator switches from a 0 to a 1 when the input crosses +v h /2. the new switching threshold becomes ?v h /2. the comparator remains in a 1 state until the ?v h /2 threshold is crossed coming from the positive direction. in this manner, noise centered on 0 v input does not cause the comparator to switch states unless it exceeds the region bounded by v h / 2 . positive feedback from the output to the input is often used to produce hysteresis in a comparator ( figure 23 ). the major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. in the adcmp552, hysteresis is generated through the programmable hysteresis pin. a resistor from the hys pin to v cci creates a current into the part that is used to g enerate hysteresis. hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. the hysteresis versus resistance curve is shown in figure 20. a current source can also be used with t he hys pin. the relationship between the current applied to the hys pin and the resulting hysteresis is shown in figure 16. figure 19 . comparator hysteresis transfer function figure 20 . comparator hysteresis transfer function minimum input slew r ate requirement as for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. this oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. analog devices recommends a slew rate of 1 v/s or faster to ensure a clean output transition. if slew rates less than 1 v/s are used, hysteresis should be ad ded to reduce the oscillation. q output input voltage 1.5v overdrive 20mv overdrive dispersion v ref v os 04722-017 output input 0 1 0v ? v h 2 +v h 2 04722-018 120 100 80 60 40 20 0 100 10 1 04722-019 r hys (k?) programmed hysteresis (mv)
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 13 of 16 typical application circuits figure 21 . high speed sampling circuits figure 22 . high speed window comparator figure 23 . adding hysteresis usi ng the hys control pin figure 24 . how to interface a pecl output to an instrument with a 50 ? to ground input adcmp551/ adcmp552/ adcmp553 + ? all resistors 50 ? outputs v in v ref latch enable inputs v cco ? 2v 04722-020 04722-021 all resistors 50 ? unless otherwise noted adcmp551/ adcmp552/ adcmp553 + ? adcmp551/ adcmp552/ adcmp553 + ? outputs +v ref ? v ref v in latch enable inputs v cco ? 2v v cco ? 2v outputs 04722-026 adcmp551/ adcmp552/ adcmp553 all resistors 50?, unless otherwise noted outputs hys v in v ref v cco ? 2.0v v cci 0? to 80k ? 04722-024 v in 50 ? 50 ? 100 ? 100 ? 50 ? 50 ? (v cco ? 2v) 2 adcmp551/ adcmp552/ adcmp553 + ?
adcmp551/adcmp552/adcmp553 data sheet rev. a | page 14 of 16 outline dimensions figure 25. 20-lead shrink small outline package [qsop] (rq-20) dimensions shown in inches and (millimeters) figure 26. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches and (millimeters) compliant to jedec standards mo-137-ad controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 20 11 10 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 08-19-2008-a compliant to jedec standards mo-137-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appr opriate for use in design. 16 9 8 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 01-28-2008-a
data sheet adcmp551/adcmp552/adcmp553 rev. a | page 15 of 16 figure 27. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adcmp551brq ?40c to +85c 16-lead shrink small outline package [qsop] rq-16 adcmp551brqz ?40c to +85c 16-lead shrink small outline package [qsop] rq-16 adcmp551brqz-reel7 ?40c to +85c 16-lead sh rink small outline package [qsop] rq-16 eval-adcmp551brqz evaluation board adcmp552brq ?40c to +85c 20-lead shrink small outline package [qsop] rq-20 adcmp552brqz ?40c to +85c 20-lead shrink small outline package [qsop] rq-20 EVAL-ADCMP552BRQZ evaluation board adcmp553brmz ?40c to +85c 8-lead mini small outline package [msop] rm-8 br53 eval-adcmp553brmz evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b
adcmp551/adcmp552/adcmp553 data sheet rev. a | page 16 of 16 notes ?2004C2013 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04722-0-6/13(a)

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